供应GTLP6C816A芯片解密设计服务
GTLP6C816A芯片解密特性描述如下：
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Features
· Interface between LVTTL and GTLP logic levels
· Designed with edge rate control circuitry to reduce out-put noise on the GTLP port
· VREF pin provides external supply reference voltage for receiver threshold adjustibility
· Special PVT compensation circuitry to provide consis-tent performance over variations of process, supply volt-age and temperature
· TTL compatible driver and control inputs
· Designed using Fairchild advanced BiCMOS technology
· Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
· Power up/down and power off high impedance for live insertion
· Open drain on GTLP to support wired-or connection
· A Port source/sink -24mA/+24mA
· B Port sink +50mA
· 1:6 fanout clock driver for TTL port
· 1:2 fanout clock driver for GTLP port
· Low voltage version of GTLP6C816
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