AT25SF321-SHD-T ADESTO 90000PCS 全新原装柜台现货
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AT25SF321
32-Mbit, 2.5V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
Features
? Single 2.5V - 3.6V Supply
? Serial Peripheral Interface (SPI) Compatible
? Supports SPI Modes 0 and 3
? Supports Dual and Quad Output Read
? 104MHz Maximum Operating Frequency
? Clock-to-Output (tV) of 6 ns
? Flexible, Optimized Erase Architecture for Code + Data Storage Applications
? Uniform 4-Kbyte Block Erase
? Uniform 32-Kbyte Block Erase
? Uniform 64-Kbyte Block Erase
? Full Chip Erase
? Hardware Controlled Locking of Protected Blocks via WP Pin
? 3 Protected Programmable Security Register Pages
? Flexible Programming
? Byte/Page Program (1 to 256 Bytes)
? Fast Program and Erase Times
? 0.7ms Typical Page Program (256 Bytes) Time
? 70ms Typical 4-Kbyte Block Erase Time
? 300ms Typical 32-Kbyte Block Erase Time
? 600ms Typical 64-Kbyte Block Erase Time
? JEDEC Standard Manufacturer and Device ID Read Methodology
? Low Power Dissipation
? 2μA Deep Power-Down Current (Typical)
? 10μA Standby current (Typical)
? 4mA Active Read Current (Typical)
? Endurance: 100,000 Program/Erase Cycles
? Data Retention: 20 Years
? Complies with Full Industrial Temperature Range
? Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
? 8-lead SOIC (150-mil and 208-mil)
? 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
? Die in Wafer Form
DS-25SF321–047F–8/2017
DeSCRJPTion
The Adesto® AT25SF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25SF321 is ideal for data storage as well, eliminating the need for
additional data storage devices.
The erase block sizes of the AT25SF321 have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register
pages can be individually locked.
1. Pin DeSCRJPTions and Pinouts
Table 1-1. Pin DeSCRJPTions
Asserted
Symbol Name and Function State Type
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected,
CS data will not be accepted on the SI pin. Low Input
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
SCK flow of data to and from the device. Command, address, and input data present on the SI pin - Input
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on
the rising edge of SCK.
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin
(I/O0) in conjunction with other pins to allow two or four bits of data on (I/O3-0) to be clocked
in on every falling edge of SCK
SI (I/O0) - Input/Output
To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as
the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it
will be referenced as I/O0
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
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Table 1-1. Pin DeSCRJPTions (Continued)
Asserted
Symbol Name and Function State Type
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in
conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every
falling edge of SCK
SO (I/O1) - Input/Output
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O1
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT: The WP pin controls the hardware locking feature of the device.
With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/O2)
and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every rising
edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an output pin
WP (I/O2) in conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on
every falling edge of SCK.
(I/O2) - Input/Output
To maintain consistency with the SPI nomenclature, the WP (I/O2) pin will be referenced as
the WP pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O2
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold Function” on page 34 for additional details on the Hold operation.
HOLD With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin
(I/O3) (I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every - Input/Output
rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an
output pin (I/O3) in conjunction with other pins to allow four bits of data on (I/O33-0) to be
clocked in on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin will be referenced
as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O3
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
VCC Operations at invalid VCC voltages may produce spurious results and should not be - Power
attempted.
GND GROUND: The ground reference for the power supply. GND should be connected to the - Power
system ground.
AT25SF321 3
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Figure 1-1. 8-SOIC (Top View) Figure 1-2. 8-UDFN (Top View)
CS 1 8 VCC
CS 1 8 VCC SO 2 7 HOLD
SO 2 7 HOLD WP 3 6 SCK
WP 3 6 SCK GND SI
GND 4 5 SI 4 5
2. Block Diagram
Figure 2-1. Block Diagram
Control and I/O Buffers
CS Protection Logic and Latches
SRAM
Data Buffer
SCK Interface
SI (I/O0) Control
And
Logic Y-Decoder Y-Gating
SO (I/O1)
Address Latch Flash
Memory
WP (I/O2) X-Decoder Array
HOLD (I/O3)
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
3. Memory Array
To provide the greatest flexibility, the memory array of the AT25SF321 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
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Figure 3-1. Memory Architecture Diagram
Block Erase Detail Page Program Detail
64KB 32KB 4KB 1-256 Byte
Block Address Page Address
Range Range
4KB 3FFFFFh – 3FF000h 256 Bytes 3FFFFFh – 3FFF00h
4KB 3FEFFFh – 3FE000h 256 Bytes 3FFEFFh – 3FFE00h
4KB 3FDFFFh – 3FD000h 256 Bytes 3FFDFFh – 3FFD00h
32KB 4KB 3FCFFFh – 3FC000h 256 Bytes 3FFCFFh – 3FFC00h
4KB 3FBFFFh – 3FB000h 256 Bytes 3FFBFFh – 3FFB00h
4KB 3FAFFFh – 3FA000h 256 Bytes 3FFAFFh – 3FFA00h
4KB 3F9FFFh – 3F9000h 256 Bytes 3FF9FFh – 3FF900h
64KB 4KB 3F8FFFh – 3F8000h 256 Bytes 3FF8FFh – 3FF800h
Sector 63 4KB 3F7FFFh – 3F7000h 256 Bytes 3FF7FFh – 3FF700h
4KB 3F6FFFh – 3F6000h 256 Bytes 3FF6FFh – 3FF600h
4KB 3F5FFFh – 3F5000h 256 Bytes 3FF5FFh – 3FF500h
32KB 4KB 3F4FFFh – 3F4000h 256 Bytes 3FF4FFh – 3FF400h
4KB 3F3FFFh – 3F3000h 256 Bytes 3FF3FFh – 3FF300h
4KB 3F2FFFh – 3F2000h 256 Bytes 3FF2FFh – 3FF200h
4KB 3F1FFFh – 3F1000h 256 Bytes 3FF1FFh – 3FF100h
4KB 3F0FFFh – 3F0000h 256 Bytes 3FF0FFh – 3FF000h
4KB 3EFFFFh – 3EF000h 256 Bytes 3FEFFFh – 3FEF00h
4KB 3EEFFFh – 3EE000h 256 Bytes 3FEEFFh – 3FEE00h
4KB 3EDFFFh – 3ED000h 256 Bytes 3FEDFFh – 3FED00h
32KB 4KB 3ECFFFh – 3EC000h 256 Bytes 3FECFFh – 3FEC00h
4KB 3EBFFFh – 3EB000h 256 Bytes 3FEBFFh – 3FEB00h
4KB 3EAFFFh – 3EA000h 256 Bytes 3FEAFFh – 3FEA00h
4KB 3E9FFFh – 3E9000h 256 Bytes 3FE9FFh – 3FE900h
64KB 4KB 3E8FFFh – 3E8000h 256 Bytes 3FE8FFh – 3FE800h
Sector 62 4KB 3E7FFFh – 3E7000h ???
4KB 3E6FFFh – 3E6000h ???
4KB 3E5FFFh – 3E5000h
32KB 4KB 3E4FFFh – 3E4000h 256 Bytes 0017FFh – 001700h
4KB 3E3FFFh – 3E3000h 256 Bytes 0016FFh – 001600h
4KB 3E2FFFh – 3E2000h 256 Bytes 0015FFh – 001500h
4KB 3E1FFFh – 3E1000h 256 Bytes 0014FFh – 001400h
4KB 3E0FFFh – 3E0000h 256 Bytes 0013FFh – 001300h
256 Bytes 0013FFh – 001300h
? ? ?
? ? ? 256 Bytes 0013FFh – 001300h
? ? ?
256 Bytes 0012FFh – 001200h
4KB 00FFFFh–00F000h 256 Bytes 0011FFh – 001100h
4KB 00EFFFh–00E000h 256 Bytes 0010FFh – 001000h
4KB 00DFFFh–00D000h 256 Bytes 000FFFh – 000F00h
32KB 4KB 00CFFFh–00C000h 256 Bytes 000CFFh – 000C00h
4KB 00BFFFh–00B000h 256 Bytes 000BFFh – 000B00h
4KB 00AFFFh–00A000h 256 Bytes 000AFFh – 000A00h
4KB 009FFFh–009000h 256 Bytes 0009FFh – 000900h
64KB 4KB 008FFFh–008000h 256 Bytes 0008FFh – 000800h
Sector 0 4KB 007FFFh–007000h 256 Bytes 0007FFh – 000700h
4KB 006FFFh–006000h 256 Bytes 0006FFh – 000600h
4KB 005FFFh–005000h 256 Bytes 0005FFh – 000500h
32KB 4KB 004FFFh–004000h 256 Bytes 0004FFh – 000400h
4KB 003FFFh–003000h 256 Bytes 0003FFh – 000300h
4KB 002FFFh–002000h 256 Bytes 0002FFh – 000200h
4KB 001FFFh–001000h 256 Bytes 0001FFh – 000100h
4KB 000FFFh–000000h 256 Bytes 0000FFh – 000000h
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